Memory controller and memory system for generating instruction set based on non-interleaving block group information

ABSTRACT

Embodiments of the present invention include a memory controller including a buffer memory configured to store program data, an instruction set configurator configured to configure an instruction set describing a procedure for programming the program data stored in the buffer memory to target memory blocks, an instruction set performer configured to sequentially perform instructions in the instruction set and generate an interrupt at a time of completion of performance of a last instruction among the instructions, and a central processing unit configured to erase the program data stored in the buffer memory when the interrupt is received from the instruction set performer. The instruction set configurator may configure the instruction set differently according to whether a non-interleaving block group exists among the target memory blocks.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a divisional application of U.S. patentapplication Ser. No. 16/745,810 filed on Jan. 17, 2020, which claimspriority under 35 U.S.C. § 119(a) to Korean patent application number10-2019-0084083, filed on Jul. 11, 2019, the entire disclosure of whichis incorporated herein by reference in its entirety.

BACKGROUND Field of Invention

The present disclosure relates to a memory controller and a memorysystem including the same, and more particularly, to a memory controllerfor performing a program operation and a memory system including thesame.

Description of Related Art

A memory system may include a memory controller and a memory device.

In response to a program request, a logical address, and data arereceived from a host, the memory controller may allocate a physicaladdress corresponding to the received logical address, and may controlthe memory device so that data is stored in the allocated physicaladdress.

SUMMARY

Embodiments of the present disclosure provide a memory controller and amemory system including the memory controller capable of enablingcompletion of a program operation.

A memory controller according to an embodiment of the present disclosuremay include a buffer memory configured to store program data, aninstruction set configurator configured to configure an instruction setdescribing a procedure for programming program data stored in the buffermemory to target memory blocks, an instruction set performer configuredto sequentially perform instructions in the instruction set and generatean interrupt at a time of completion of performance of a lastinstruction among the instructions and a central processing unitconfigured to erase the program data stored in the buffer memory whenthe interrupt is received from the instruction set performer, whereinthe instruction set configurator configures the instruction setdifferently according to whether a non-interleaving block group existsamong the target memory blocks.

A memory system according to an embodiment of the present disclosure mayinclude a first die including a non-interleaving block group, a seconddie including an interleaving block group and a memory controllerconfigured to, transmit first partial data of first data from a buffermemory to the first die to program the first partial data into thenon-interleaving block group, transmit, after transmitting the firstpartial data, second data from the buffer memory to the second die toprogram the second data into the interleaving block group, transmit,after transmitting the second data, second partial data of the firstdata from the buffer memory to the first die to program the secondpartial data into the non-interleaving block group, and erase, aftertransmitting the second partial data, the first and second data storedin the buffer memory.

A memory system according to an embodiment of the present disclosure mayinclude a memory device including first and second dies sharing a singlechannel, the first die including first and second memory blocks within asingle plane of the first die, and the second die including a group ofmemory blocks within different planes of the second die, a bufferconfigured to buffer first to third pieces of data and a controllerconfigured to, control the memory device to perform a program operationof sequentially storing the first to third pieces of data respectivelyinto the first memory block, the group of memory blocks and the secondmemory block and remove the first to third pieces of data from thebuffer upon completion of the program operation, wherein the programoperation is performed on the group of memory blocks according to aplane interleaving scheme.

According to embodiments of the present invention, since program datastored in the buffer memory may be erased quickly within a limit thatenables completion of a program operation, a capacity of the buffermemory may be quickly secured.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a memory system according to anembodiment of the present disclosure.

FIG. 2 is a diagram illustrating exemplary components of arepresentative die of dies shown in FIG. 1 .

FIGS. 3 and 4 are diagrams illustrating a memory cell array and a pagebuffer group shown in FIG. 2 .

FIG. 5 is a diagram illustrating a super block and an interleaving blockgroup.

FIGS. 6 and 7 are diagrams illustrating a replacement super block and anon-interleaving block group.

FIG. 8 is a diagram illustrating a memory controller shown in FIG. 1 .

FIG. 9 is a diagram illustrating a descriptor.

FIGS. 10 to 12 are diagrams illustrating an instruction set.

FIGS. 13 to 16 are diagrams illustrating another example of the memorysystem including the memory controller shown in FIGS. 1 and 8 .

DETAILED DESCRIPTION

Referring to FIG. 1 , a memory system 2000, according to an embodimentof the present disclosure, may include a memory device 2200 in whichdata is stored and a memory controller 2100 controls the memory device2200 according to a request of a host 1000.

The host 1000 may be any suitable device or system that stores data inthe memory system 2000 or retrieves data from the memory system 2000.For example, the host 1000 may include a computer, a portable digitaldevice, a tablet, a digital camera, a digital audio player, atelevision, a wireless communication device, and/or a cellular phone,but embodiments of the present disclosure are not limited thereto.

The memory controller 2100 may control overall operations of the memorysystem 2000. The memory controller 2100 may perform various operationsaccording to a request from the host 1000. For example, the memorycontroller 2100 may perform a program operation, a read operation, anerase operation, or the like on the memory device 2200. During theprogram operation, the memory controller 2100 may transmit a programcommand, an address, data, and the like to the memory device 2200.During the read operation, the memory controller 2100 may transmit aread command, an address, and the like to the memory device 2200 andreceive read data from the memory device 2200. During the eraseoperation, the memory controller 2100 may transmit an erase command, anaddress, and the like to the memory device 2200.

The memory device 2200 may perform the program operation, the readoperation, the erase operation, and the like under control of the memorycontroller 2100. The memory device 2200 may include one or more dies,e.g., dies D11 to D1 i, D21 to D2 i, and Dk1 to Dki. k and i are naturalnumbers. For example, each of the dies D11 to D1 i, D21 to D2 i, and Dk1to Dki may be implemented as a volatile memory device in which storeddata is lost when power supply is cut off, or as a non-volatile memorydevice in which stored data is retained even when the power supply iscut off. For example, the dies D11 to D1 i, D21 to D2 i, and Dk1 to Dkimay be NAND flash memory devices.

The dies D11 to D1 i, D21 to D2 i, and Dk1 to Dki may be connected tothe controller 2100 through a plurality of channels CH1 to CHk. Forexample, the dies D11 to D1 i may be connected to the first channel CH1,the dies D21 to D2 i may be connected to the second channel CH2, and thedies Dk1 to Dki may be connected to the k-th channel CHk.

Each of the dies D11 to D1 i, D21 to D2 i, and Dk1 to Dki may receive aprogram command, an address, and data from the memory controller 2100,and store data according to the program command and the address. Each ofthe dies D11 to D1 i, D21 to D2 i, and Dk1 to Dki may perform the readoperation according to the read command and the address received fromthe memory controller 2100, and may provide read data to the memorycontroller 2100. Each of the dies D11 to D1 i, D21 to D2 i, and Dk1 toDki may perform the erase operation according to an erase command and anaddress received from the memory controller 2100.

FIG. 2 is a diagram illustrating a configuration of a representative dieof the dies shown in FIG. 1 .

Referring to FIG. 2 , a die Dki may include a memory cell array 2210 inwhich data is stored, and a peripheral circuit that includes a voltagegenerator 2220, a row decoder 2230, a page buffer group 2240, a columndecoder 2250, and an input/output circuit 2260 for performing a program,read, or erase operation, and control logic 2270 that controls theperipheral circuit.

The memory cell array 2210 may include a plurality of planes. Each ofthe planes may include a plurality of memory blocks in which data isstored. Each of the memory blocks may include a plurality of memorycells. The memory cells may be implemented in a two-dimensionalstructure in which the memory cells are arranged in parallel to asubstrate or in a three-dimensional structure in which the memory cellsare stacked on the substrate in a vertical direction. The memory cellarray 2210 will be described in more detail with reference to FIGS. 3and 4 .

The voltage generator 2220 may generate operation voltages Vop necessaryfor various operations in response to an operation signal OPS. Forexample, the operation voltage Vop may include a program voltage, averify voltage, a read voltage, a pass voltage, and/or an erase voltage.The voltage generator 2220 may output the generated operation voltageVop to the row decoder 2230.

The row decoder 2230 may transmit the operation voltage Vop throughlocal lines connected to a memory block selected according to a rowaddress RADD among memory blocks included in the memory cell array 2210.

The page buffer group 2240 may include a plurality of page buffersconnected to bit lines. The page buffer group 2240 may include pagebuffers or multi-level buffers corresponding to the planes included inthe die Dki, respectively. The page buffers or the multi-level buffersmay temporarily store data during program, read, and verify operationsin response to a control signal PBSIG. Each of the page buffers or themulti-level buffers may include a plurality of latches for temporarilystoring data during the program, read, and verify operations. The pagebuffer group 2240 is described in more detail with reference to FIGS. 3and 4 .

The column decoder 2250 may transfer data received from the input/outputcircuit 2260 to the page buffer group 2240 in response to a columnaddress CADD during the program operation, or may transfer data receivefrom the page buffer group 2240 to the input/output circuit 2260 duringthe read operation.

The input/output circuit 2260 may be connected to the controller 2100 ofFIG. 1 through input/output lines included in the channel CHk toinput/output a command CMD, an address ADD, and data DATA. For example,during the program operation, the input/output circuit 2260 may transmitthe command CMD and the address ADD received from the controller 2100 tothe control logic 2270, and may transmit the data DATA to the columndecoder 2250. The address ADD input to the input/output circuit 2260 maybe a physical address output by the controller 2100. For example, duringthe read operation, the input/output circuit 2260 may output the dataDATA received from the column decoder 2250 to the controller 2100through the input/output lines.

The control logic 2270 may control the peripheral circuit and itsindividual components 2220, 2230, 2240, 2250, and 2260 in response tothe command CMD and the address ADD received through the input/outputcircuit 2260. The control logic 2270 may generate the operation signalOPS and the control signal PBSIG in response to the command CMD, and maygenerate the row address RADD and the column address CADD in response tothe address ADD. The row address RADD may be output to the row decoder2230, and the column address CADD may be output to the column decoder2250.

FIG. 3 is a diagram illustrating the memory cell array and the pagebuffer group shown in FIG. 2 .

The memory cell array 2210 may include a plurality of planes. In FIG. 3, an example in which two planes, that is, a Plane 1 2212 and a Plane 22214 are included in the memory cell array 2210 is shown, butembodiments of the present disclosure are not limited thereto. Forexample, three or more planes may be included in the memory cell array2210.

Each of the planes 2212 and 2214 may include a plurality of memoryblocks. In FIG. 3 , k memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK2 k are included in the planes 2212 and 2214, respectively, where k isan integer of 2 or more. While FIG. 3 shows that each of the planes 2212and 2214 have the same number of memory blocks, the present invention isnot limited to that configuration; the planes need not have the samenumber of memory blocks in all embodiments.

Each of the memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 k mayinclude a plurality of physical pages. Each of the memory blocks may ormay not have the same number of pages. Each of the physical pages mayinclude a plurality of memory cells.

Each of the physical pages may include one logical page. For example,when the memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 k are SLCblocks operating in a single-level cell (SLC) mode, each of the physicalpages in the memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 k mayinclude one logical page.

The page buffer group 2240 may include page buffers corresponding toeach of the planes included in the memory cell array 2210. For example,when the two planes 2212 and 2214 are included in the memory cell array2210, the page buffer group 2240 may include a page buffer 1 2242corresponding to the Plane 1 2212 and a page buffer 2 2244 correspondingto the Plane 2 2214.

Each of the page buffers 2242 and 2244 may store one logical page data.One logical page data may include as many data bits as the number ofmemory cells included in one physical page.

The logical page data stored in the page buffer 1 2242 may be programmedin a physical page in any one of the memory blocks BLK 11 to BLK 1 k inthe Plane 1 2212, and the logical page data stored in the page buffer 22244 may be programmed in a physical page in any one of the memoryblocks BLK 21 to BLK 2 k in the Plane 2 2214. When a plane interleavingmethod is used during the program operation, the logical page datastored in the page buffer 1 2242 and the logical page data stored in thepage buffer 2 2244 may be simultaneously programmed.

FIG. 4 is a diagram illustrating examples of the memory cell array andthe page buffer group shown in FIG. 2 .

The memory cell array 2210 may include a plurality of planes. In FIG. 4, an example in which two planes, that is, a Plane 1 2212 and a Plane 22214 are included in the memory cell array 2210 is shown, butembodiments of the present disclosure are not limited thereto. Forexample, three or more planes may be included in the memory cell array2210.

Each of the planes 2212 and 2214 may include a plurality of memoryblocks. In FIG. 4 , k memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK2 k are included in the planes 2212 and 2214, respectively, where k isan integer of 2 or more. While FIG. 4 shows that each of the planes 2212and 2214 have the same number of memory blocks, the present invention isnot limited to that configuration; the planes need not have the samenumber of memory blocks in all embodiments.

Each of the memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 k mayinclude a plurality of physical pages. Each of the memory blocks may ormay not have the same number of pages. Each of the physical pages mayinclude a plurality of memory cells.

Each of the physical pages may include a plurality of logical pages. Forexample, when the memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 kare m-bit MLC blocks operating in an m-bit multi-level cell (MLC) mode,each of the physical pages in the memory blocks BLK 11 to BLK 1 k andBLK 21 to BLK 2 k may include m logical pages, where m is a naturalnumber. In FIG. 4 , as an example, a case where the memory blocks BLK 11to BLK 1 k and BLK 21 to BLK 2 k are 2-bit MLC blocks, that is, each ofthe memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 k includes twological pages (a least significant bit (LSB) page and a most significantbit (MSB) page) is shown, but embodiments of the present disclosure arenot limited thereto. For example, the memory blocks BLK 11 to BLK 1 kand BLK 21 to BLK 2 k may be 3-bit MLC blocks (which may be referred toas TLC blocks) or 4-bit MLC blocks (which may be referred to as QLCblocks).

The page buffer group 2240 may include page buffers corresponding to theplanes included in the memory cell array 2210, respectively. Forexample, when the two planes 2212 and 2214 are included in the memorycell array 2210, the page buffer group 2240 may include a page buffer 12242 corresponding to the Plane 1 2212 and a page buffer 2 2244corresponding to the Plane 2 2214.

Each of the page buffers 2242 and 2244 may include a plurality oflogical page buffers. In FIG. 4 , as an example, the page buffer 2242includes two logical page buffers, that is, an LSB page buffer 2242 aand an MSB page buffer 2242 b and the page buffer 2244 includes twological page buffers, that is, an LSB page buffer 2244 a and an MSB pagebuffer 2244 b, but embodiments of the present disclosure are limitedthereto. For example, when the memory blocks BLK 11 to BLK 1 k and BLK21 to BLK 2 k are m-bit MLC blocks, each of the page buffers 2242 and2244 may include m logical page buffers for the m logical pages. Forexample, when the memory blocks BLK 11 to BLK 1 k and BLK 21 to BLK 2 kare 3-bit MLC blocks, each of the page buffers 2242 and 2244 may includethree logical page buffers, and when the blocks BLK 11 to BLK 1 k andBLK 21 to BLK 2 k are 4-bit MLC blocks, each of the page buffers 2242and 2244 may include four logical page buffers.

Each of the logical page buffers 2242 a, 2242 b, 2244 a, and 2244 b maystore one logical page data. For example, each of the logical pagebuffers 2242 a and 2244 a may store LSB page data, and each of thelogical page buffers 2242 b and 2244 b may store MSB page data. Onelogical page data may include the same number of data bits as there arememory cells in one physical page.

The plurality of pieces of logical page data (LSB page data and MSB pagedata) stored in the page buffer 1 2242 may be programmed in a physicalpage in any of the memory blocks BLK 11 to BLK 1 k in the Plane 1 2212,and the plurality of pieces of logical page data (LSB page data and MSBpage data) stored in the page buffer 2 2244 may be programmed in aphysical page in any of the memory blocks BLK 21 to BLK 2 k in the Plane2 2214. When a plane interleaving method is used during the programoperation, the pieces of the logical page data stored in the page buffer1 2242 and the pieces of the logical page data stored in the page buffer2 2244 may be simultaneously programmed.

In the following description, it is assumed that the memory blocks areSLC blocks, but the embodiments of the present disclosure may be equallyapplied to the case where the memory blocks are m-bit MLC blocks.

FIG. 5 is a diagram illustrating a super block and an interleaving blockgroup.

In FIG. 5 , as an example, dies Dk1 and Dk2 connected to the channel CHkare shown among the dies shown in FIG. 1 .

The memory controller 2100 may configure a super block by logicallyconnecting memory blocks in the plurality of dies Dk1 and Dk2 in orderto improve parallel processing performance of the memory system 2000.

As an example, one super block may include one memory block per plane ineach of the dies Dk1 and Dk2. For example, a memory block BLK 11 inPlane 1 of the die Dk1, a memory block BLK 21 in Plane 2 of the die Dk1,a memory block BLK 31 in Plane 3 of the die Dk2, and a memory block BLK41 in Plane 4 of the die Dk2 may configure one super block, Super BLK1.In the same principle, another super block, super BLK2, may beconfigured.

The memory blocks BLK 13, BLK 23, BLK 33, and BLK 43 may be used toreplace a bad memory block among memory blocks in the super blocks.

The dies Dk1 and Dk2 may operate in a die interleaving method. That is,the dies Dk1 and Dk2 may operate in parallel with each other. Forexample, the program operation may be performed on the die DK2 while theprogram operation is performed on the die Dk1.

Each of the super blocks super BLK 1 and super BLK 2 may includeinterleaving block groups. Each of the interleaving block groups mayinclude as many memory blocks as the number of planes included in onedie, and may include one of the memory blocks included in each of theplanes. That is, each of the interleaving block groups may includememory blocks included in different planes among memory blocks includedin the same die. For example, the memory block BLK 11 included in Plane1 of the die Dk1 and the memory block BLK 21 included in Plane 2 of thedie Dk1 may configure one interleaving block group.

The memory blocks included in the same interleaving block group mayoperate in a plane interleaving method. That is, the program operationmay be performed in parallel on the memory blocks included in the sameinterleaving block group. For example, the program operation may besimultaneously performed on the memory block BLK 11 and the memory blockBLK 21 included in the same interleaving block group.

FIGS. 6 and 7 are diagrams illustrating a replacement super block and anon-interleaving block group.

When a bad memory block occurs among the memory blocks configuring thesuper block, the memory controller 2100 replaces the bad memory blockwith one of the memory blocks included in the same die as the bad memoryblock to configure the replacement super block. The memory block thatreplaces the bad memory block may be referred to as a replacement memoryblock.

In an embodiment, the memory controller 2100 may replace the bad memoryblock in one plane with a replacement memory block in the same plane. Insuch a case, the interleaving block group may be maintained. An exampleof a case where the interleaving block group is maintained is shown inFIG. 6 .

In FIG. 6 , an example in which a replacement super block 2 (Replacementsuper BLK2) is generated by replacing a bad memory block BLK 22 in thedie Dk1 with a replacement memory block BLK 23 is shown. In the exampleshown in FIG. 6 , the memory block BLK 12 and the replacement memoryblock BLK 23 in the replacement super block 2 belong to differentplanes, i.e., they belong to Plane 1 and Plane 2 respectively.Therefore, the memory block BLK 12 and the replacement memory block BLK23 may operate in the plane interleaving method, and the memory blockBLK 12 and the replacement memory block BLK 23 may be referred to as theinterleaving block group.

In an embodiment, the memory controller 2100 may replace the bad memoryblock in a plane with a replacement memory block in a different plane.In such a case, the interleaving block group may not be maintained. Anexample of a case where the interleaving block group is not maintainedis shown in FIG. 7 .

In FIG. 7 , an example in which a replacement super block 2 is generatedby replacing a bad memory block BLK 22 in the die Dk1 with a replacementmemory block BLK 13 is shown. In the example shown in FIG. 7 , thememory block BLK 12 and the replacement memory block BLK 13 in thereplacement super block 2 belong to the same plane, i.e., Plane 1.Therefore, the memory block BLK 12 and the replacement memory block BLK13 may not operate in the plane interleaving method, and the memoryblock BLK 12 and the replacement memory block BLK 13 may be referred toas a non-interleaving block group.

The non-interleaving block group may include as many memory blocks asthere are planes in one die, and the memory blocks included in thenon-interleaving block group may belong to the same plane.

FIG. 8 is a diagram illustrating an example of the memory controllershown in FIG. 1 .

The memory controller 2100 may include a host interface 2110, a centralprocessing unit 2120, a memory interface 2130, a buffer memory 2140, anerror correction circuit 2150, and/or an internal memory 2160. The hostinterface 2110, the memory interface 2130, the buffer memory 2140, theerror correction circuit 2150, and the internal memory 2160 may becontrolled by the central processing unit 2120.

The host interface 2110 may transfer a program request, a read request,an erase request, and the like received from the host 1000 to thecentral processing unit 2120. The host interface 2110 may store programdata received from the host 1000 in the buffer memory 2140.

The host interface 2110 may communicate with the host 1000 using any ofvarious interface protocols. For example, the host interface 2110 maycommunicate with the host 100 using a non-volatile memory express(NVMe), a peripheral component interconnect-express (PCI-E), an advancedtechnology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA),a universal serial bus (USB), a multi-media card (MMC), an enhancedsmall disk interface (ESDI), integrated drive electronics (IDE), amobile industry processor interface (MIPI), a universal flash storage(UFS), a small computer small interface (SCSI), and/or a serial attachedSCSI (SAS), but embodiments of the present disclosure are not limitedthereto.

The central processing unit 2120 may include an address allocator 2120a, a descriptor generator 2120 b, and a buffer memory manager 2120 c.

The address allocator 2120 a may determine a storage area in whichprogram data stored in the buffer memory 2140 is to be stored, andallocate a virtual address corresponding to the determined storage areacorresponding to the program data. Here, the storage area in which theprogram data is to be stored may correspond to one super block, and thevirtual address may be information for identifying a super block. Forexample, the virtual address may include information on the die and/orinformation on the super block. The address allocator 2120 a may providethe virtual address corresponding to the program data to the descriptorgenerator 2120 b.

The descriptor generator 2120 b may generate a descriptor that serves asa work order in which items of work required to program the program datastored in the buffer memory 2140 into target memory blocks (for example,one super block) are described. The descriptor may include operationinformation, data position information, and/or the virtual addressprovided from the address allocator 2120 a. The descriptor generator2120 b may insert information indicating an interrupt after the lastwork among the work items in the descriptor. An example of thedescriptor is described later with reference to FIG. 9 .

The buffer memory manager 2120 c may monitor the program data stored inthe buffer memory 2140. In a case where enough program data is collectedin the buffer memory 2140 to fill one storage area (for example, onesuper block), the buffer memory manager 2120 c may so inform the addressallocator 2120 a. When an interrupt is received from the memoryinterface 2130, the buffer memory manager 2120 c may erase the programdata stored in the buffer memory 2140.

The memory interface 2130 may include a memory block manager 2130 a, aninstruction set configurator 2130 b, and an instruction set performer2130 c.

The memory block manager 2130 a may manage the super block and thereplacement super block. For example, the memory block manager 2130 amay manage a mapping relationship between a virtual address and aphysical address. For example, the physical address may correspond tomemory blocks in the super block or memory blocks included in thereplacement super block.

When a bad memory block exists among the memory blocks included in thesuper block, the memory block manager 2130 a may replace the bad memoryblock with the replacement memory block.

The memory block manager 2130 a may manage information on whether thememory blocks in the replacement super block are an interleaving blockgroup or a non-interleaving block group. For example, the memory blockmanager 2130 a may manage information on which die among the memoryblocks in the replacement super block is an interleaving block group ora non-interleaving block group.

The memory block manager 2130 a may monitor the descriptor received fromthe descriptor generator 2120 b and check whether the virtual address inthe descriptor corresponds to the super block or the replacement superblock. When the virtual address in the descriptor corresponds to thereplacement super block, the memory block manager 2130 a may checkwhether the non-interleaving block group exists in the replacement superblock.

When the virtual address in the descriptor corresponds to a super blockor a replacement super block that does not include a non-interleavingblock group, the memory block manager 2130 a may provide informationindicating that a non-interleaving block group does not exist to theinstruction set configurator 2130 b.

When the virtual address in the descriptor corresponds to thereplacement super block including the non-interleaving block group, thememory block manager 2130 a may provide information indicating where thenon-interleaving block group is positioned to the instruction setconfigurator 2130 b.

The instruction set configurator 2130 b may receive the descriptor fromthe descriptor generator 2120 b and configure an instruction set basedon the received descriptor. The instruction set configurator 2130 b mayprovide the configured instruction set to the instruction set performer2130 c.

In the instruction set, the procedure required to perform the work itemsdescribed in the descriptor may be described. For example, in theinstruction set, instructions to program the program data stored in thebuffer memory 2140 into target memory blocks (for example, the superblock or the replacement super block) may be described.

The instruction set configurator 2130 b may configure the instructionset differently according to whether the non-interleaving block groupexists among the target memory blocks (for example, the super block orthe replacement super block).

For example, it is assumed that the target memory blocks include anon-interleaving block group in a Die 1 and an interleaving block groupin a Die 2. In this case, the instruction set configurator 2130 b mayseparately configure first instructions corresponding to a first memoryblock among the memory blocks in the non-interleaving block group in theDie 1 and second instructions corresponding to a second memory blockamong the memory blocks in the non-interleaving block group in the Die1. In addition, the instruction set configurator 2130 b may configurethird instructions corresponding to the interleaving block group in theDie 2 separately from the first and second instructions. The instructionset configurator 2130 b may configure the instruction set such that thesecond instructions are positioned after, and hence performed after, thethird instructions.

For example, it is assumed that the target memory blocks include a firstinterleaving block group in the Die 1 and a second interleaving blockgroup in the Die 2. In this case, the instruction set configurator 2130b may separately configure instructions corresponding to the firstinterleaving block group and instructions corresponding to the secondinterleaving block group.

An example of the instruction set is described later with reference toFIGS. 10 to 12 .

The instruction set performer 2130 c may receive the instruction setfrom the instruction set configurator 2130 b and sequentially performthe instructions as ordered in the received instruction set. Forexample, the instruction set performer 2130 c may transmit a command, aphysical address, and program data to dies including the target memoryblocks according to the instructions described in the instruction set.In addition, when a holding instruction is included in a firstinstruction set corresponding to a particular die, the instruction setperformer 2130 c may hold performing a second instruction set alsocorresponding to that die such that access thereto is suspended untilcompletion of the performing of the first instruction set.

The instruction set performer 2130 c may generate and provide aninterrupt to the central processing unit 2120 when performance of thelast instruction among the instructions in the instruction set iscompleted.

The buffer memory 2140 may temporarily store data while the memorycontroller 2100 controls the memory device 2200. For example, the buffermemory 2140 may store the program data.

The error correction circuit 2150 may perform error correction encodingduring the program operation and may perform error correction decodingduring the read operation.

The internal memory 2160 may be used as storage for storing variouspieces of information required for the operation of the memorycontroller 2100.

FIG. 9 is a diagram illustrating an example of a descriptor.

The descriptor may include operation information, data positioninformation, and/or a virtual address.

The operation information may indicate whether an operation to beperformed is a program operation, a read operation, an erase operation,or a standby operation. In FIG. 9 , an example in which information DataIn indicating the program operation and information Tprog indicating thestandby operation is shown.

The data position information may indicate a position where the programdata is stored on the buffer memory. In FIG. 9 , an example in whichinformation pDATA(1-2) as to where first data of the program data isstored and information pDATA(3-4) as to where second data of the programdata is stored is shown.

The virtual address may include information corresponding to the superblock and/or die. In FIG. 9 , an example in which index information SB1corresponding to the super block and index information Die 1 and Die 2corresponding to a die is shown.

A first syntax (Data In/pDATA(1-2)/Die 1/SB1) of the descriptor mayindicate an operation of transmitting the first data stored in thestorage position pDATA(1-2) of the buffer memory to the super block SB 1included in the Die 1.

A second syntax (Tprog/Die 1) of the descriptor may indicate anoperation of waiting for a time during which the first data transmittedto the Die 1 is programmed.

A third syntax (Data In/pDATA(3-4)/Die 2/SB1) of the descriptor mayindicate an operation of transmitting the second data stored in thestorage position pDATA(3-4) of the buffer memory to the super block 1 SB1 included in the Die 2.

A fourth syntax (Tprog/Die 2/ITR) of the descriptor may indicate anoperation of waiting for a time during which the second data transmittedto the Die 2 is programmed.

The fourth syntax (Tprog/Die 2/ITR) which is the last syntax of thedescriptor may include information (ITR) indicating to generate aninterrupt when the performance of the instruction corresponding to acorresponding syntax is completed.

FIG. 10 is a diagram illustrating an instruction set.

FIG. 10 shows a case where there is no non-interleaving block groupamong the target memory blocks.

The instruction set may include instruction(s) corresponding to eachsyntax included in the descriptor. For example, the instruction set mayinclude instructions 1-1, 1-2, and 1-3 corresponding to a first syntax(Data In/pDATA(1-2)/Die 1/SB1) of the descriptor, an instruction 2corresponding to a second syntax (Tprog/Die 1) of the descriptor,instructions 3-1, 3-2, and 3-3 corresponding to a third syntax (DataIn/pDATA(3-4)/Die 2/SB1) of the descriptor, and an instruction 4corresponding to a fourth syntax (Tprog/Die 2/ITR) of the descriptor.The last instruction 4 among the instructions in the instruction set mayinclude information (ITR) indicating to generate the interrupt whenperformance of the last instruction 4 is completed, as described in thedescriptor.

A command CMD1, an address ADD1-2, and data DATA 1-2 may be transmittedto the Die 1 according to the instructions 1-1, 1-2, and 1-3, and thestandby operation may be performed until the program operation iscompleted in the Die 1.

Similarly, a command CMD2, an address ADD3-4 and data DATA 3-4 may betransmitted to the Die 2 according to the instructions 3-1, 3-2, and3-3, and the standby operation may be performed until the programoperation is completed in the Die 2. The interrupt may occur when thestandby operation is completed. Therefore, the program data may beerased from the buffer memory.

FIG. 11 is a diagram illustrating an exemplary instruction set.

FIG. 11 shows a case where a non-interleaving block group exists amongtarget memory blocks. Description overlapping with that of FIG. 10 isomitted.

When the non-interleaving block group exists among the target memoryblocks, instructions corresponding to the memory blocks included in thenon-interleaving block group may be separately configured. In FIG. 11 ,as an example, a case where the memory blocks in the Die 1 is anon-interleaving block group is shown.

The instruction set may include instructions 1-1, 1-2, 1-3, 5-1, 5-2,and 5-3 corresponding to a first syntax (Data In/pDATA(1-2)/Die 1/SB1)of the descriptor, instructions 2 and 6 corresponding to a second syntax(Tprog/Die 1) of the descriptor, instructions 3-1, 3-2, and 3-3corresponding to a third syntax (Data In/pDATA(3-4)/Die 2/SB1) of thedescriptor, and an instruction 4 corresponding to a fourth syntax(Tprog/Die 2/ITR) of the descriptor. The instruction 4 positioned in themiddle of the instructions in the instruction set may includeinformation (ITR) indicating to generate the interrupt when performanceof the instruction 4 is completed, as described in the descriptor.

A command CMD1, an address ADD1, and data DATA 1 may be transmitted tothe Die 1 according to the instructions 1-1, 1-2, and 1-3, and thestandby operation may be performed until the program operation on thedata DATA 1 is completed in the Die 1.

Similarly, a command CMD2, an address ADD3-4 and data DATA 3-4 may betransmitted to the Die 2 according to the instructions 3-1, 3-2, and3-3, and the standby operation may be performed until the programoperation on the data DATA 3-4 is completed in the Die 2.

Similarly, a command CMD3, an address ADD2 and data DATA 2 may betransmitted to the Die 1 according to the instructions 5-1, 5-2, and5-3, and the standby operation may be performed until the programoperation on the data DATA 2 is completed in the Die 1.

Since the instruction set includes the information ITR indicating togenerate the interrupt when the performance of the instruction 4 iscompleted, the interrupt occurs when the program operation on the dataDATA 3-4 is completed. Accordingly, the program data may be erased fromthe buffer memory.

However, when the performance of the instruction 4 is completed,completion of the instructions 5-1, 5-2, 5-3, and 6 may not be ensured.For example, the performance of the instruction 4 may be completed in astate in which the data DATA 2 is not transmitted to the Die 1 or theprogram operation on the data DATA 2 is not completed. That is, theinterrupt may occur in a state in which the data DATA 2 is nottransmitted to the Die 1 or the program operation on the data DATA 2 isnot completed. Therefore, a problem may arise in which the program datastored in the buffer memory is erased in a state in which the data DATA2 is not transmitted or the program data stored in the buffer memory iserased in a state in which the program operation on the data DATA 2fails, and thus retransmission of the data DATA 2 is required.

FIG. 12 is a diagram illustrating an exemplary instruction set.

FIG. 12 shows a case where a non-interleaving block group exists amongthe target memory blocks. Description overlapping that of FIG. 11 isomitted.

When the non-interleaving block group exists among the target memoryblocks, instructions corresponding to the memory blocks in thenon-interleaving block group may be separately configured. In FIG. 12 ,as an example, a case where the memory blocks included in the Die 1 is anon-interleaving block group is shown.

The instruction set may include instructions 1-1, 1-2, 1-3, 5-1, 5-2,and 5-3 corresponding to a first syntax (Data In/pDATA(1-2)/Die 1/SB1)of the descriptor, instructions 2 and 6 corresponding to a second syntax(Tprog/Die 1) of the descriptor, instructions 3-1, 3-2, and 3-3corresponding to a third syntax (Data In/pDATA(3-4)/Die 2/SB1) of thedescriptor, and an instruction 4 corresponding to a fourth syntax(Tprog/Die 2/ITR) of the descriptor.

In contrast to the embodiment of FIG. 11 , in the embodiment of FIG. 12, the instruction 6 positioned at the end of the instructions in theinstruction set may include information indicating to generate aninterrupt when performance of the instruction 6 is completed. Inaddition, the instruction 4 corresponding to the fourth syntax(Tprog/Die 2/ITR) of the descriptor may not include the informationindicating to generate the interrupt when the performance of theinstruction 4 is completed.

Similarly to the embodiment described with reference to FIG. 11 , in theembodiment of FIG. 12 , the instructions 1-1, 1-2, 1-3, the instruction2, the instructions 3-1, 3-2, and 3-3, the instruction 4, theinstructions 5-1, 5-2, and 5-3 and the instruction 6 may be sequentiallyperformed.

Since the instruction set includes the information ITR indicating togenerate the interrupt when the performance of the instruction 6 iscompleted, the interrupt occurs when the program operation on the dataDATA 2 is completed. Accordingly, the program data may be erased fromthe buffer memory. That is, according to the embodiment shown in FIG. 12, all work items described in the descriptor may be successfullycompleted.

Among the instructions corresponding to the Die 1, the instruction 2 mayinclude information (HOLD) for prohibiting access to the Die 1 by aninstruction in an instruction set other than the instruction set that iscurrently being performed. Therefore, data other than the data DATA 2may be prevented from being transmitted to the Die 1 before theperformance of the instructions 5-1, 5-2, 5-3, 6 is completed.

FIG. 13 is a diagram illustrating another example of the memory systemincluding the memory controller shown in FIGS. 1 and 8 .

Referring to FIG. 13 , the memory system 30000 may be implemented as acellular phone, a smart phone, a tablet, a personal computer (PC), apersonal digital assistant (PDA), or a wireless communication device.The memory system 30000 may include the memory device 2200 and thememory controller 2100 capable of controlling the operation of thememory device 2200.

The memory controller 2100 may control a data access operation, forexample, a program operation, an erase operation, a read operation, orthe like, of the memory device 2200 under control of a processor 3100.

Data programmed in the memory device 2200 may be output through adisplay 3200 under the control of the memory controller 2100.

A radio transceiver 3300 may transmit and receive a radio signal throughan antenna ANT. For example, the radio transceiver 3300 may convert aradio signal received through the antenna ANT into a signal that may beprocessed by the processor 3100. Therefore, the processor 3100 mayprocess the signal output from the radio transceiver 3300 and transmitthe processed signal to the memory controller 2100 or the display 3200.The memory controller 2100 may transmit the signal processed by theprocessor 3100 to the memory device 2200. In addition, the radiotransceiver 3300 may convert a signal output from the processor 3100into a radio signal, and output the radio signal to an external devicethrough the antenna ANT. An input device 3400 may be a device capable ofinputting a control signal for controlling the operation of theprocessor 3100 or data to be processed by the processor 3100. The inputdevice 3400 may be implemented as a pointing device such as a touch pador a computer mouse, a keypad, or a keyboard. The processor 3100 maycontrol an operation of the display 3200 so that data output from thememory controller 2100, data output from the radio transceiver 3300, ordata output from the input device 3400 is output through the display3200.

According to an embodiment, the memory controller 2100 capable ofcontrolling the operation of memory device 2200 may be implemented as apart of the processor 3100 and may be implemented as a chip separatefrom the processor 3100.

FIG. 14 is a diagram illustrating another example of the memory systemincluding the memory controller shown in FIGS. 1 and 8 .

Referring to FIG. 14 , the memory system 40000 may be implemented as apersonal computer (PC), a tablet, a net-book, an e-reader, a personaldigital assistant (PDA), a portable multimedia player (PMP), an MP3player, or an MP4 player.

The memory system 40000 may include the memory device 2200 and thememory controller 2100 capable of controlling a data process operationof the memory device 2200.

A processor 4100 may output data stored in the memory device 2200through a display 4300, according to data input through an input device4200. For example, the input device 4200 may be implemented as a pointdevice such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memorysystem 40000 and control the operation of the memory controller 2100.According to an embodiment, the memory controller 2100 capable ofcontrolling the operation of memory device 2200 may be implemented as apart of the processor 4100 or may be implemented as a chip separate fromthe processor 4100.

FIG. 15 is a diagram illustrating another example of the memory systemincluding the memory controller shown in FIGS. 1 and 8 .

Referring to FIG. 15 , the memory system 50000 may be implemented as animage processing device, for example, a digital camera, a portable phoneprovided with a digital camera, a smart phone provided with a digitalcamera, or a tablet provided with a digital camera.

The memory system 50000 includes the memory device 2200 and the memorycontroller 2100 capable of controlling a data process operation, forexample, a program operation, an erase operation, or a read operation,of the memory device 2200.

An image sensor 5200 of the memory system 50000 may convert an opticalimage into digital signals. The converted digital signals may betransmitted to a processor 5100 or the memory controller 2100. Undercontrol of the processor 5100, the converted digital signals may beoutput through a display 5300 or stored in the memory device 2200through the memory controller 2100. In addition, data stored in thememory device 2200 may be output through the display 5300 under thecontrol of the processor 5100 or the memory controller 2100.

According to an embodiment, the memory controller 2100 capable ofcontrolling the operation of memory device 2200 may be implemented as apart of the processor 5100 or may be implemented as a chip separate fromthe processor 5100.

FIG. 16 is a diagram illustrating another example of the memory systemincluding the memory controller shown in FIGS. 1 and 8 .

Referring to FIG. 16 , the memory system 70000 may be implemented as amemory card or a smart card. The memory system 70000 may include thememory device 2200, the memory controller 2100, and a card interface7100.

The memory controller 2100 may control data exchange between the memorydevice 2200 and the card interface 7100. According to an embodiment, thecard interface 7100 may be a secure digital (SD) card interface or amulti-media card (MMC) interface, but is not limited thereto.

The card interface 7100 may interface data exchange between a host 60000and the memory controller 2100 according to a protocol of the host60000. According to an embodiment, the card interface 7100 may support auniversal serial bus (USB) protocol, and an interchip (IC)-USB protocol.Here, the card interface 7100 may refer to hardware capable ofsupporting a protocol that is used by the host 60000, software installedin the hardware, or a signal transmission method.

When the memory system 70000 is connected to a host interface 6200 ofthe host 60000 such as a PC, a tablet, a digital camera, a digital audioplayer, a mobile phone, a console video game hardware, or a digitalset-top box, the host interface 6200 may perform data communication withthe memory device 2200 through the card interface 7100 and the memorycontroller 2100 under control of a microprocessor 6100.

While embodiments of the present invention have been illustrated anddescribed, the present invention is not limited to the disclosedembodiments nor to any specific details in the description. As thoseskilled in the art will appreciate in light of the present disclosure,various modifications may be made to any of the disclosed embodimentsthat still fall within the scope of the present invention. Thus, thepresent invention encompasses all modifications and variations that fallwithin the scope of the claims.

What is claimed is:
 1. A memory system comprising: a first die includinga non-interleaving block group; a second die including an interleavingblock group; and a memory controller configured to: transmit firstpartial data of first data from a buffer memory to the first die toprogram the first partial data into the non-interleaving block group,transmit, after transmitting the first partial data, second data fromthe buffer memory to the second die to program the second data into theinterleaving block group, transmit, after transmitting the second data,second partial data of the first data from the buffer memory to thefirst die to program the second partial data into the non-interleavingblock group, and erase, after transmitting the second partial data, thefirst and second data stored in the buffer memory.
 2. The memory systemof claim 1, wherein the memory controller comprises: an instruction setconfigurator configured to configure an instruction set describing aprocedure for sequentially programming the first and second data; and aninstruction set performer configured to sequentially performinstructions in the instruction set, to transmit the first and seconddata to the first and second dies.
 3. The memory system of claim 2,wherein the instruction set performer generates an interrupt at a timeof completion of performance of a last instruction among theinstructions in the instruction set, and wherein the last instruction isrelated to the second partial data.
 4. The memory system of claim 3,wherein the memory controller comprises a central processing unitconfigured to erase the first and second data stored in the buffermemory when the interrupt is received from the instruction setperformer.
 5. The memory system of claim 2, wherein the instruction setconfigurator separately configures first instructions corresponding tothe first partial data and second instructions corresponding to thesecond partial data.
 6. The memory system of claim 5, wherein theinstruction set configurator configures third instructions correspondingto the second data separately from the first and second instructions. 7.The memory system of claim 6, wherein the instruction set configuratorconfigures the instruction set such that the second instructions are setto be performed after the third instructions.
 8. The memory system ofclaim 5, wherein the instruction set performer accesses the first dieaccording to the first instructions, the second instructions, or aseparate instruction that is not included in the instruction set, andholds the separate instruction before performance of the secondinstructions is completed.
 9. The memory system of claim 1, whereinmemory blocks of the non-interleaving block group are included in thesame plane of the first die, and wherein memory blocks of theinterleaving block group are included in different planes of the seconddie.
 10. A memory system comprising: a memory device including first andsecond dies sharing a single channel, the first die including first andsecond memory blocks within a single plane of the first die, and thesecond die including a group of memory blocks within different planes ofthe second die; a buffer configured to buffer first to third pieces ofdata; and a controller configured to: control the memory device toperform a program operation of sequentially storing the first to thirdpieces respectively into the first memory block, the group and thesecond memory block; and remove the first to third pieces from thebuffer upon completion of the program operation, wherein the programoperation is performed on the group according to a plane interleavingscheme.